| | The first meeting with the course students should be on Thursday, February 17, 2011, 10:00 - 14:00,
in the Levi Bldg, floor Alef, in the Projects Lab of Doron.
  Short Course Syllabus Word document News forum Full Course Syllabus PDF document
____Design-For-Testability & JTAG Technologies _____________ Dr. Ami Gorodetsky ______________________ 4 credit points
 __________________ Course # 67703 
Design-For-Testability (DFT) is a key concern during hardware development and a major concern for design engineers when designing device (chip, IC, ASIC, SOC), circuit board (PCB) or a system. DFT techniques are design methods specifically employed to ensure that an electronic device, board or system is readily testable, and suitable for many kinds of on-board and on-system activity (CPLD and FPGA configuration, Flash programming, etc). The testability of a circuit is an abstract concept that deals with a variety of the costs associated with testing and design. Today, design and testing are no longer separate issues. The emphasis on the quality of the shipped product, coupled with the growing complexity of circuit board designs, requires testing issues to be considered as early as possible in the design process, so that the design can be modified to streamline and economize the testing process.
Boundary-Scan (JTAG) technologies, as well as IEEE 1149.1- and IEEE 1149.6-compatible board designs provide overwhelming competitive benefits for board and system manufacturers. These benefits come in the form of faster time-to-market, shorter programming time, and lower tester cost. Faster time-to-market results come from time savings in two traditional areas that typically act as gates to the new product introduction process: prototype debug time and test program development time. Faster programming time results from the automated programming that can be achieved with BS-compatible designs. The new IEEE 1149.4 Std. “Mixed Signal Test Bus” (more popularly known as “Analog Boundary-Scan”), the new IEEE 1149.6 Std. “Testing Advanced I/O” (more popularly known as “AC EXTEST”), as well as the newest 1149.7 Std. “2-pin JTAG” and many others are covered by this course too.
Modern electronic testing has a more than forty year history. Test professionals hold regular large conferences and numerous workshops, have a peer-reviewed journal, and there are hundreds of published works on the subject. Still, a full course on modern electronic testing, or a partial course on DFT and JTAG technologies, is offered only at a few universities worldwide, mostly by professors who have a research interest in this area.
The Hebrew University of Jerusalem one-semester course No. 67703 (56 hours) is aimed at undergraduate students in the electrical and electronic engineering programs, as well as QA students, who may have an interest in the practical problems of competing successfully in the face of rapidly evolving and dynamic Israeli High-Tech sector. Since many of these changes affect our ability to do testing and hence cost-effective production, the “Design-For-Testability and JTAG Technologies” course attempts to educate its students about proper test and testability goals and successful attainment of those goals. The mixture of theory and practical demonstrations, as well as exhaustive lab work with Flynn onTAP Test Station and real-life demo circuit boards are as close to the practice as possible. The course colour and animated slides are presented in English. Explanations and verbal communication are provided in Hebrew.
Semester Score List:
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Recommended Bibliography: 
M.Bushnell, V.Agrawal , “Essentials of Electronic Testing for Digital, Memory & Mixed-Synal VLSI Citcuits”, KAP, 3rd Printing
K.Parker , “The Boundary-Scan Handbook. Analog and Digital”, KAP, 2003
Ami Gorodetsky , “Design-For-Testability and JTAG Technologies”, HUJI Students Workbook & Course Manual, 2011 (web)
Recommended Web Links:
- DFT Glossary of Terms PDF document
- Midterm exam papers PDF document
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About the Lecturer 
Dr. Ami Gorodetsky has over thirty years of industry and university experience (both internationally and domestically) in the development and deployment of electronic testing strategies. Dr. Gorodetsky is also a recognized and accomplished academic in the fields of circuit and device Design-for-Testability (DFT) methodology and JTAG technologies (1149.1, 1149.4, 1149.6, 1149.7, 1149.8.1, 1532, 1500, 1687, P1581, etc.) implementation.
He holds a B.S., a M.S. and a Ph.D. degrees in Electrical Engineering. He has held many test engineering positions in a variety of industries, incl. defense electronics, telecommunications, and semiconductors. Ami is currently the Chief Technologist of the StarTest company (www.Start-Test.com), Technical Director of the JTAG.Test company (www.JTAG-Test.ru), and a senior lecturer at the Hi-Tech College (Herzlia). Over the years Ami has taught dozens of courses in-house for Israeli hi-tech companies, and through the University extension programs. His research interests are in the structural digital, analog, and mixed-signal testing, JTAG technologies, as well as Design-For-Testability (DFT) and Design-For-Security (DFS) methodologies for chips and boards. Ami has published numerous papers and patents related to electronic testing.
 Brief Publication List file
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